Tera-scale Computing

By Lin Chao
Publisher and Editor, Intel Technology Journal

Engineers and researchers in Intel's advanced research labs have been investigating ideas associated with tera-scale (10¹²) computing power (trillions of operations per second) to help solve highly complex problems, do critical mathematical analysis, or run computationally intensive applications more efficiently and in real time. This investigation is based on the growing need for intensive computation, visualization, or manipulation and management of massive amounts of data. We anticipate trillions of calculations to occur within a second (teraflops) to achieve performance and productivity to run these complex scientific and commercial applications.

Our devices will be able to comprehend data better and use this knowledge to act on our behalf. To do so, computers must have the ability to think in terms of models—digital "models" of people, places, and information.

The theme of the eight papers in this Q3'07 Intel Technology Journal is "Tera-scale Computing Research." Future tera-scale computers will be based on 10s to 100s of integrated processor cores. We discuss the research work in progress at Intel's labs. The first six papers look at tera-scale architecture research and discuss both its inherent challenges and some potential solutions to those challenges. In particular, the first paper looks at tera-scale architecture and design tradeoffs. With its very high level of integration and the presence of heterogeneous building blocks, a modular and scalable on-chip interconnect is required. Based on the organization, architectural building blocks, and physical design constraints, we expect ring, 2D-mesh, or similar topologies to be an attractive option. The second paper reviews future tera-scale architecture's inclusion of accelerator cores alongside Intel^® Architecture cores. We show how an accelerator exoskeleton can provide a shared Virtual Memory (VM) heterogeneous multi-threaded programming paradigm for these accelerators by adding extensions to the CPU instruction set and software tools that have an Intel Architecture (IA) look-n-feel. The third paper describes the package technology required for tera-scale computing needs. The scope and focus of the paper are primarily design and electrical performance challenges. We discuss a roadmap that evolves from today's off-package memory to complex on-package integrated memory architectures. The fourth paper presents the design and implementation of a runtime environment for tera-scale platforms. We discuss the design and implementation of a Many-Core RunTime (McRT) environment—a prototype tera-scale runtime environment. We present simulation results from a tera-scale simulator to show that McRT enables excellent scalability on tera-scale platforms. The fifth paper proposes a hardware scheme to accelerate dynamic task scheduling. To harness the computing resources of tera-scale computing architecture cores, applications must expose their thread-level parallelism to the hardware. We explore hardware schedulers that do this for large-scale multiprocessor systems: they decompose parallel sections of programs into many tasks and let a task scheduler dynamically assign tasks to threads. In the sixth paper we start by highlighting tera-scale potential in datacenter environments. We show how a multi-tier datacenter workload that required tens (to hundreds) of platforms in the past can potentially map onto one (or a few) single-socket tera-scale platforms running VMs and thereby create Datacenter-on-Chip (DoC) architectures.

The remaining papers then review tera-scale applications on media mining and physical simulations. Media mining can help us more easily retrieve, organize, and manage the exponentially growing amount of media data. The seventh paper explores several usage models in media mining. To efficiently use the processing power provided by multi-core processors, we studied common parallelization schemes and propose a general parallel framework for these media-mining applications. And finally, in the eighth paper of this Q3'07 Intel Technology Journal, we study physical simulation applications in two broad categories: production physics and game physics. After parallelization, the benchmark applications achieve parallel scalabilities of thirty to sixty times on a simulated chip-multiprocessor with 64 cores.

So, how does tera-scale computing affect our lives at home? In our future homes, we will use tera-scale computers for better personal media management, immersive and personalized entertainment, educational collaborations and personal health visualization and management, to name a few examples. I am especially excited that this issue of the Intel Technology Journal has this topic as its focus: I am part of the team working on tera-scale computing research in Intel's labs. Tera-scale computing will play a major role in shaping Intel's computer architecture for the next decade. We are excited to continue our work to realize these possibilities.